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| description the LCX017DLT is a 4.6cm diagonal active matrix tft-lcd panel addressed by polycrystalline silicon super thin film transistors with a built-in peripheral driving circuit. use of three LCX017DLT panels provides a full-color representation. the striped arrangement suitable for data projectors is capable of displaying fine text and vertical lines. the adoption of dms (dual metal shield) structure realizes a high luminance screen. and new cross talk free and ghost free structures contribute to high picture quality. this panel has a polysilicon tft high-speed scanner and built-in function to display images up/down and/or right/left inverse. the built-in 5v interface circuit leads to lower voltage of timing and control signals. the panel contains an active area variable circuit which supports s-xga 5:4 and pc-98 8:5 data signals by changing the active area according to the type of input signal. features number of active dots: 786,432 (1.8 type, 4.6cm in diagonal) accepts the computer requirements of xga, svga, vga, ntsc and pal supports sxga with simple display high optical transmittance: 23% (typ.) new high light resistance dms (dual metal shield) structure adopted new cross talk free and ghost free structures high contrast ratio with normally white mode: 350 (typ.) built-in h and v drivers (built-in input level conversion circuit, 5v driving possible) up/down and/or right/left inverse display function antidust glass used element structure dots: 1024 (h) 768 (v) = 786,432 built-in peripheral driver using polycrystalline silicon super thin film transistors applications liquid crystal data projectors liquid crystal rear-projector tvs, etc. ?1 LCX017DLT e00212a15 4.6cm (1.8 type) black-and-white lcd panel sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. ? the company's name and product's name in this data sheet is a trademark or a registered trademark of each company.
?2 LCX017DLT 18 com vsig6 vsig5 vsig4 vsig3 vsig2 vsig1 vss vv dd hv dd enb dwn pcg vck vst rgt blk hck2 hck1 hst v ss gl psig 17 20 19 21 22 23 16 2 24 hb vb 25 29 26 28 15 30 27 v ss gr 9 12 11 10 8 7 4 3 5 13 6 14 31 vsig7 vsig8 vsig9 vsig10 vsig11 vsig12 1 h shift register (bidirectional scanning) up/down and/or right/left inversion control circuit v shift register (bidirectional scanning) precharge control circuit com pad v shift register (bidirectional scanning) side-black control circuit black frame control circuit black frame control circuit input signal level shifter circuit block diagram 3 LCX017DLT absolute maximum ratings (v ss = 0v) h driver supply voltage hv dd 1.0 to +20 v v driver supply voltage vv dd 1.0 to +20 v common pad voltage com 1.0 to +17 v h shift register input pin voltage hst, hck1, hck2, 1.0 to +17 v rgt v shift register input pin voltage vst, vck, pcg, 1.0 to +17 v blk, enb, dwn hb, vb video signal input pin voltage sig1 to 12, psig 1.0 to +15 v operating temperature ? topr 10 to +70 c storage temperature tstg 30 to +85 c ? panel temperature inside the antidust glass operating conditions (v ss = 0v) supply voltage hv dd 13.5 0.5v vv dd 15.5 0.5v input pulse voltage (vp-p of all input pins except video signal and uniformity improvement signal input pins) vin 5.0 0.5v 4 LCX017DLT pin description pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 psig v ss gr vsig1 vsig2 vsig3 vsig4 vsig5 vsig6 vsig7 vsig8 vsig9 vsig10 vsig11 vsig12 hv dd rgt hst hck2 hck1 v ss v ss gl blk enb vck vst dwn hb vb pcg vv dd com test symbol description uniformity improvement signal gnd for right v gate video signal 1 to panel video signal 2 to panel video signal 3 to panel video signal 4 to panel video signal 5 to panel video signal 6 to panel video signal 7 to panel video signal 8 to panel video signal 9 to panel video signal 10 to panel video signal 11 to panel video signal 12 to panel power supply for h driver drive direction pulse for h shift register (h: nomal, l: reverse) start pulse for h shift register drive clock pulse for h shift register drive 2 clock pulse for h shift register drive 1 gnd (h, v drivers) gnd for left v gate input for pc98 mode enable pulse for gate selection clock pulse for v shift register drive start pulse for v shift register drive drive direction pulse for v shift register (h: nomal, l: reverse) display switch for s-xga display switch for pc98 mode improvement pulse for uniformity power supply for v driver common voltage of panel test pin, leave this pin open 5 LCX017DLT input equivalent circuit to prevent static charges, protective diodes are provided for each pin except the power supplies. in addition, protective resistors are added to all pins except the video signal inputs. all pins are connected to v ss with a high resistor of 1m ? (typ.). the equivalent circuit of each input pin is shown below: (resistance value: typ.) input lc level conversion circuit (single-phase input) 2.5k ? 2.5k ? vv dd input level conversion circuit (single-phase input) 250 ? 250 ? hv dd input level conversion circuit (single-phase input) 2.5k ? 2.5k ? hv dd input hv dd 250 ? 250 ? 250 ? 250 ? level conversion circuit (2-phase input) input hv dd signal line (1) vsig1 to vsig12, psig (2) hck1, hck2 (3) rgt (4) hst (5) pcg, vck (6) vst, blk, enb, dwn, hb, vb (7) com 1m ? input 1m ? 1m ? 1m ? level conversion circuit (single-phase input) 250 ? 250 ? vv dd input 1m ? 1m ? ? 1m ? vv dd 1m ? input 1m ? (8) hv dd , v ss gr, v ss gl, vv dd are all vss. ? dwn is 400k ?. 6 LCX017DLT input signals 1. input signal voltage conditions (v ss = 0v) item h shift register input voltage hst, hck1, hck2, rgt (low) (high) (low) (high) vhil vhih vvil vvih vvc vsig vcom vpsigb vpsigg 0.5 4.5 0.5 4.5 6.9 vvc 4.5 vvc 0.5 vvc 4.4 vvc 1.8 0.0 5.0 0.0 5.0 7.0 7.0 vvc 0.4 vvc 4.5 vvc 1.9 0.4 5.5 0.4 5.5 7.1 vvc + 4.5 vvc 0.3 vvc 4.6 vvc 2.0 v v v v v v v v v shift register input voltage hb, vb, blk, vst, vck, pcg, enb, dwn video signal center voltage video signal input range ? 1 common voltage of panel ? 2 uniformity improvement signal input voltage (psig) ? 3 symbol min. typ. max. unit ? 1 input video signal shall be symmetrical to vvc. ? 2 the typical value of the common pad voltage may lower its suitable voltage according to the set construction to use. in this case, use the voltage of which has maximum contrast as typical value. when the typical value is lowered, the maximum and minimum values may lower. ? 3 input a uniformity improvement signal psig in the same polarity with video signals vsig1 to vsig12 and which is symmetrical to vvc. psig wave form is 2 steps like below, in the upper chart, upper shows signal level of the 1st step, lower shows signal level of the 2nd step. also, the rising and falling of psig are synchronized with the rising of pcg pulse, and the rise time trpsig and fall time tfpsig are suppressed within 450ns (as shown in a diagram below). level conversion circuit the LCX017DLT has a built-in level conversion circuit in the clock input unit on the panel. the input signal level increases to hv dd or vv dd . the v cc of external ics are applicable to 5 0.5v. trpsig tfpsig vvc psig pcg 90% 10% prg ? 4 psigg psigb input waveform of uniformity improvement signal psig ? 4 prg shows the time of the 1st step of psig signal, and it is not input to the panel. 7 LCX017DLT 2. clock timing conditions (ta = 25 c) (xga mode: fhckn = 3.9mhz, fvck = 34.3khz) ? 5 hckn means hck1 and hck2. ? 6 blk is the timing during pc98 mode, which keeps "h" level in other modes. hst rise time hst fall time hst data set-up time hst data hold time hckn rise time ? 5 hckn fall time ? 5 hck1 fall to hck2 rise time hck1 rise to hck2 fall time vst rise time vst fall time vst data set-up time vst data hold time vck rise time vck fall time enb rise time enb fall time horizontal video period completed to enb fall time enb rise to prg ? 4 fall time enb fall to pcg rise time enb pulse width pcg rise time pcg fall time pcg rise to vck rise/fall time pcg fall to horizontal video period start time pcg pulse width prg ? 4 rise to pcg rise time prg ? 4 fall to pcg fall time prg ? 4 pulse width blk rise time blk fall time blk rise to enb fall time blk fall to pcg rise time trhst tfhst tdhst thhst trhckn tfhckn to1hck to2hck trvst tfvst tdvst thvst trvck tfvck trenb tfenb tdenb toprg ? 4 topcg twenb trpcg tfpcg tovck tovideo twpcg topcgr topcgf twprg ? 4 trblk tfblk toenb topcg 55 55 15 15 2 2 760 110 830 1650 100 170 1400 10 570 830 2 1 65 65 0 0 7 7 800 120 1000 0 200 1700 0 700 1000 1 0 30 30 75 75 30 30 15 15 100 100 12 12 100 100 100 100 130 30 30 100 10 100 100 0 1 ns s ns item symbol min. typ. max. unit hst hck vst vck enb pcg blk ? 5 prg ? 4 s 8 LCX017DLT ? 7 definitions: the right-pointing arrow ( ) means +. the left-pointing arrow ( ) means . the black dot at an arrow ( ) indicates the start of measurement. 9 LCX017DLT 10 LCX017DLT item symbol waveform conditions prg ? 4 fall to pcg fall time prg ? 4 topcgf prg ? 4 pulse width twprg ? 4 50% ? 7 prg ? 4 pcg topcgf 50% 50% twprg ? 4 topcgr 50% ? 7 blk 50% topcg 50% toenb 50% 50% pcg enb blk blk rise time trblk blk fall time tfblk blk rise to enb fall time toenb blk fall to pcg rise time topcg 90% 10% 10% 90% tfblk trblk ? 8 pcg input pin and prg ? 4 should be "h" level during the horizontal 1h period, where the above blk is low more than 10ns. ? 8 twpcg 50% 50% tovideo pcg ? 7 50% vck h. blanking period h. video period tovck pcg ? 8 pcg rise time trpcg pcg fall time tfpcg pcg rise to vck rise/fall time tovck pcg fall to horizontal video period start time pcg pulse width prg ? 4 rise to pcg rise time tovideo twpcg topcgr 90% 10% 10% 90% pcg trpcg tfpcg 11 LCX017DLT electrical characteristics (ta = 25 c, hv dd = 13.5v, vv dd = 15.5v) 1. horizontal drivers item input pin capacitance hckn hst input pin current hck1 hck2 hst rgt video signal input pin capacitance current consumption chckn chst csig ih hck1 = gnd hck2 = gnd hst = gnd rgt = gnd hckn: hck1, hck2 (3.9mhz) 500 1000 500 150 30 35 220 390 120 30 200 14.0 35 40 250 20.0 pf pf a a a a pf ma symbol min. typ. max. unit condition 2. vertical drivers item input pin capacitance vck vst input pin current vck,pcg vst, enb, dwn, blk, hb, vb current consumption cvck cvst iv 1000 150 15 15 180 40 4.0 20 20 6.0 pf pf a a ma symbol min. typ. max. unit condition 3. total power consumption of the panel 4. pin input resistance item pin v ss input resistance rpin 0.4 1 m ? symbol min. typ. max. unit item com pin capacitance com 20 25 nf symbol min. typ. max. unit item total power consumption of the panel pwr 250 400 mw symbol min. typ. max. unit vck = gnd, pcg = gnd vst, enb, dwn,blk, hb vb = gnd vck: (34.3khz) 5. uniformity improvement signal item input pin capacitance for uniformity improvement signal cpsigo 13 nf symbol min. typ. max. unit 16 6. com pin capacitance 12 LCX017DLT reflection preventive processing when a phase substrate which rotates the polarization axis is used to adjust to the polarization direction of a polarization screen or prism, use a phase substrate with reflection preventive processing on the surface. this prevents characteristic deterioration caused by luminous reflection. electro-optical characteristics (xga mode) item contrast ratio 25 c 25 c 25 c 60 c 25 c 60 c 25 c 60 c 0 c 25 c 0 c 25 c 60 c 25 c 25 c cr t rv 90-25 gv 90-25 bv 90-25 rv 90-60 gv 90-60 bv 90-60 rv 50-25 gv 50-25 bv 50-25 rv 50-60 gv 50-60 bv 50-60 rv 10-25 gv 10-25 bv 10-25 rv 10-60 gv 10-60 bv 10-60 ton0 ton25 toff0 toff25 f yt60 ctk 200 20 0.7 0.9 1.0 0.7 0.8 1.0 1.1 1.2 1.3 1.1 1.2 1.3 1.6 1.7 1.8 1.6 1.7 1.8 350 23 1.1 1.3 1.4 1.1 1.2 1.4 1.5 1.6 1.7 1.5 1.6 1.7 2.0 2.1 2.2 2.0 2.1 2.2 37 17 100 30 65 0 1.5 1.6 1.7 1.4 1.5 1.7 1.8 1.9 2.0 1.8 1.9 2.0 2.3 2.4 2.5 2.3 2.4 2.5 80 40 200 70 40 5 1 2 3 4 5 6 7 % v ms db s % optical transmittance v-t characteristics v 90 v 50 on time off time v 10 response time flicker image retention time cross talk symbol measurement method min. typ. max. unit 13 LCX017DLT 14 LCX017DLT 2. optical transmittance optical transmittance (t) is given by the following formula (2). white luminance t = 100 [%] ... (2) luminance of light source "white luminance" means the maximum luminance on the screen at the input signal amplitude v ac = 0.5v on measurement system i . 3. v-t characteristics v-t characteristics, or the relationship between signal amplitude and the transmittance of the panels, are measured by system ii by inputting the same signal amplitude v ac to each input pin. v 90 , v 50 , and v 10 correspond to the voltages which define 90%, 50%, and 10% of transmittance respectively. 4. response time response time ton and toff are defined by formulas (5) and (6) respectively. ton = t1 ton ...(5) toff = t2 toff ...(6) t1: time which gives 10% transmittance of the panel. t2: time which gives 90% transmittance of the panel. the relationships between t1, t2, ton and toff are shown in the right figure. 90 50 10 v 90 v 50 v 10 v ac signal amplitude [v] transmittance [%] input signal voltage (waveform applied to the measured pixels) 4.5v 0.5v 7.0v 0v optical transmittance output waveform 100% 90% 10% 0% ton t1 ton toff t2 toff 15 LCX017DLT 5. flicker flicker (f) is given by formula (7). dc and ac (xga/ntsc: 30hz, rms, pal: 25hz, rms) components of the panel output signal for gray raster ? mode are measured by a dc voltmeter and a spectrum analyzer in system ii . f [db] = 20log { ac component } ...(7) dc component 6. image retention time apply the monoscope signal to the lcd panel for 60 minutes and then change this signal to the gray scale of vsig = 7.0 v ac (v ac : 3 to 4v). judging by sight at the v ac that holds the maximum image retention, measure the time till the residual image becomes indistinct. ? monoscope signal conditions: vsig = 7.0 4.5 or 2.0 [v] (shown in the right figure) vcom = 6.6v 7. cross talk cross talk is determined by the luminance differences between adjacent areas represented by wi' and wi (i = 1 to 4) around a black window (vsig = 4.5 v/1v). cross talk value ctk = 100 [%] ? each input signal voltage for gray raster mode is given by vsig = 7.0 v 50 [v] where: v 50 is the signal amplitude which gives 50% of transmittance in v-t characteristics. black level white level vsig waveform 7.0v 0v 4.5v 2.0v 4.5v 2.0v w1 w1 ' w3 w3 ' w2 w2 ' w4 ' w4 wi' wi wi 16 LCX017DLT viewing angle characteristics (typical value) 90 270 180 0 theta phi 70 50 100 150 200 250 aa aa 50 aa aa 20 aa aa 10 cr = 5 10 30 180 x 270 y 0 90 z 0 marking measurement method 17 LCX017DLT 1. dot arrangement the dots are arranged in a stripe. the shaded area is used for the dark border around the display. 4 dots 1032dots 4 dots 772 dots 2 dots 1024 dots (effective 36.86mm) 768 dots (effective 27.65mm) gate sw active area photo-shielding gate sw 2 dots 18 LCX017DLT 2. lcd panel operations [description of basic operations] a vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse to every 768 gate lines sequentially in a single horizontal scanning period. (xga mode) a horizontal driver, which consists of horizontal shift registers, gates and cmos sample-and-hold circuits, applies selected pulses to every 1024 signal electrodes sequentially in a single horizontal scanning period. these pulses are used to supply the sampled video signal to the row signal lines. vertical and horizontal shift registers address one pixel, and then thin film transistors (tfts; two tfts) turn on to apply a video signal to the dot. the same procedures lead to the entire 768 1024 dots to display a picture in a single vertical scanning period. the data and video signals shall be input with the 1h-inverted system. [description of operating mode] this lcd panel can change the active area by displaying a black frame to support various computer or video signals. the active area is switched by hb, vb and blk. however, the center of the screen is not changed. the active area setting modes are shown below. hb vb blk screen aspect ratio hh h l h h ? 1 4:3 1024 768 5:4 ? 2 960 768 8:5 1024 640 l h ? 1 input blk pulse (refer to drive waveform and vertical blanking period of pc98 made). ? 2 for only aspect ratio 5:4 mode, set psig and com voltage as shown below. the value of psigg and com voltage is typical value. it is necessary to optimize the voltage for each set construction. psig com prg ? 3 vvc + 4.5 [v] vvc + 1.0 [v] vcom + 2.0 vvc 4.5 [v] vvc vvc 1.0 [v] vcom vcom 2.0 psig b psig g ? 3 prg shows the time of the 1st step of psig signal, and it is not input to the panel. 19 LCX017DLT (1) vertical direction display cycle (dwn = h, l) rgt mode right scan left scan h l dwn mode down scan up scan h l this lcd panel has the following functions to easily apply to various uses, as well as various broadcasting systems. right/left inverse mode up/down inverse mode these modes are controlled by two signals (rgt and dwn). the right/left and/or up/down setting modes are shown below. right/left and/or up/down mean the direction when the pin 1 marking is located at the right side with the pin block upside. to locate the active area in the center of the panel in each mode, polarity of the start pulse and clock phase for both the h and v systems must be varied. the phase relationship between the start pulse and the clock for each mode is shown below. vd 12 vertical display cycle 768h vck 34 765 766 767 768 vst vd 12 vertical display cycle 640h vck 34 637 638 639 640 vst (1.2) pc98 (1.1) xga, sxga 20 LCX017DLT (2) horizontal direction display cycle (2.1.1) xga, pc98 (rgt = h) 1234 horizontal display cycle hst hck1 83 84 85 86 hck2 hd (2.1.2) xga, pc98 (rgt = l) horizontal display cycle hst hck1 12 3 4 83 84 85 86 hck2 hd (2.2.1) sxga (rgt = h) horizontal display cycle hst hck1 12 3 4 77 78 79 80 hck2 hd (2.2.2) sxga (rgt = l) horizontal display cycle hst hck1 77 78 79 80 hck2 hd 1234 21 LCX017DLT (3) vertical blanking cycle of pc98 mode the input waveforms of pcg, prg ? 1 and psig should be changed as shown below when blk pulse is input. blk vck enb pcg prg ? 1 psig vertical blanking cycle ? 1 prg shows the period of psig black level, it is not input to the panel. 22 LCX017DLT 3. 12-dot simultaneous sampling the horizontal shift register samples signals vsig1 to vsig12 simultaneously. this requires phase matching between signals vsig1 to vsig12 to prevent the horizontal resolution from deteriorating. thus, phase matching between each signal is required using an external signal delaying circuit before applying the video signal to the lcd panel. the block diagram of the delaying procedure using the sample-and-hold method is as follows. the following phase relationship diagram indicates the phase setting for right scan (rgt = high level). for left scan (rgt = low level), the phase settings for signals vsig1 to vsig12 are exactly reversed. vsig1 s/h s/h s/h s/h s/h s/h s/h s/h s/h s/h s/h s/h ck12 vsig2 vsig3 vsig4 vsig5 vsig6 vsig7 vsig8 vsig9 vsig10 vsig11 vsig12 3 4 5 6 7 8 9 10 11 12 13 14 LCX017DLT s/h ck11 s/h ck10 s/h ck9 s/h ck8 s/h ck7 s/h ck6 s/h ck5 s/h ck4 s/h ck3 s/h ck2 s/h ck1 vsig1 vsig2 vsig3 vsig4 vsig5 vsig6 vsig7 vsig8 vsig9 vsig10 vsig11 vsig12 23 LCX017DLT 24 LCX017DLT display system block diagram an example of display system is shown below. cxa3512r s/h driver cxa3512r s/h driver lcx017 6 6 cxa3512r s/h driver cxa3512r s/h driver lcx017 6 6 cxa3512r s/h driver cxa3512r s/h driver lcx017 6 6 cxd3500r timing generator cxa2111r gamma cxd3503r color shading correction cxa3106aq pll l.p.f. vst prg, clp mclk/2 dsync enb, prg, frp timing pulses r g b hsync vsync 25 LCX017DLT notes on handling (1) static charge prevention be sure to take the following protective measures. tft-lcd panels are easily damaged by static charges. a) use non-chargeable gloves, or simply use bare hands. b) use an earth-band when handling. c) do not touch any electrodes of a panel. d) wear non-chargeable clothes and conductive shoes. e) install conductive mats on the working floor and working table. f) keep panels away from any charged materials. g) use ionized air to discharge the panels. (2) protection from dust and dirt a) operate in a clean environment. b) when delivered, the panel surface (glass panel) is covered by a protective sheet. peel off the protective sheet carefully so as not to damage the glass panel. c) do not touch the glass panel surface. the surface is easily scratched. when cleaning, use a clean- room wiper with isopropyl alcohol. be careful not to leave a stain on the surface. d) use ionized air to blow dust off the glass panel. (3) other handling precautions a) do not twist or bend the flexible pc board especially at the connecting region because the board is easily deformed. b) do not drop the panel. c) do not twist or bend the panel or panel frame. d) keep the panel away from heat sources. e) do not dampen the panel with water or other solvents. f) avoid storing or using the panel at a high temperature or high humidity, which may result in panel damages. g) minimum radius of bending curvature for a flexible substrate must be 1mm. h) torque required to tighten screws on a panel must be 0.294n m or less. i) use appropriate filter to protect a panel. j) do not pressure the portion other than mounting hole (cover). 26 LCX017DLT package outline unit: mm active area incident light incident light polarizing axis 1 4 3 5 2 7 9 8 6 description molding material outside frame reinforcing board reinforcing material f p c no 1 2 3 4 5 6 cover 1 7 8 cover 2 9 glass 1 glass 2 mass 25g the rotation angle of the active area relative to h and v is 1 . electrode (enlarged) 0.5 0.1 0.5 0.15 4.0 0.4 pin32 pin1 (27.6) 50.0 0.15 40.0 0.1 5.0 0.1 25.0 0.25 (36.9) 25.0 0.25 3.0 0.1 50.0 0.1 56.0 0.15 107.6 1.4 (51.6) 2.2 0.1 2.35 0.1 5.4 0.1 16.5 0.05 2.2 0.1 4-r3.0 thickness of the connector 0.3 0.05 3- 2.3 0.05 c0.8 output light polarizing axis p 0.5 0.02 31 = 15.5 0.03 0.35 0.03 sony corporation |
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